1. Field of the Invention
The present invention relates to integrated circuitries in a semiconductor substrate, and in particular to a concept of compensating the negative influence of a mechanical stress component in the semiconductor substrate on the parameter accuracy and parameter stability of the circuitry integrated on the semiconductor substrate.
2. Description of Prior Art
Integrated circuitries, or integrated circuits (ICs), are typically mounted in packages to protect the sensitive integrated circuitries from environmental influences. However, one disadvantageous side effect that may be observed is that accommodating and mounting the integrated circuitry in a package exerts considerable mechanical stress on the semiconductor material, and thus on the semiconductor substrate of the integrated circuitry.
This applies, in particular, to low-cost package shapes configured as mass articles, such as to such package forms wherein a sealing compound is injected around the integrated circuitry. The sealing compound hardens by cooling down to ambience temperature from a temperature of about 150° C.-185° C. Since the semiconductor material of the integrated circuitry and the plastic sealing material of the package surrounding the integrated circuitry exhibit thermal expansion coefficients which do not match, during the cooling to ambient temperature, i.e. room temperature, the plastic materials will shrink more and exert essentially non-reproducible mechanical stress on the semiconductor material of the integrated circuitry. The plastic material generally has a higher thermal expansion coefficient than the semiconductor material of the integrated circuitry, the semiconductor materials used mostly being silicon or even germanium, gallium arsenide (GaAs), InSb, InP, etc.
The mechanical stress, or the mechanical strain, present in the semiconductor material of the semiconductor substrate and acting on the integrated circuitry is generally hard to reproduce because the mechanical stress depends on the combination of the materials used for the semiconductor substrate and for the sealing compound, and, in addition, on the processing parameters, such as the hardening temperature and hardening period of the sealing compound of the package of the integrated circuitry.
Various piezo effects present in the semiconductor material, such as the piezoresistive effect, piezo MOS effect, piezojunction effect, piezo Hall effect and piezo-tunnel effect, also influence important electrical and/or electronic parameters of the integrated circuitry due to mechanical stress of the integrated circuitry which is operating. In connection with the description below, the generic term “piezo effects” is to generally refer to the changes of electrical and/or electronic parameters of the circuitry integrated in the semiconductor material under the influence of mechanical stress in the semiconductor material.
Mechanical stress in the semiconductor material results in a change in the properties of the charge carriers with regard to the charge-carrier transport, such as mobility, collision time, scattering factor, Hall constant, etc.
In more general words, the piezoresistive effect determines how the specific ohmic resistance of the respective semiconductor material will behave under the influence of mechanical stress. The piezojunction effect results, among other things, in changes in the characteristics of diodes and bipolar transistors. The piezo Hall effect describes the dependence of the Hall constant of the semiconductor material on the mechanical stress condition in the semiconductor material.
The piezo-tunnel effect occurs at reversely operated, highly doped, shallow lateral pn junctions. This current is dominated by band-to-band tunnel effects and is also dependent on stresses.
In connection with the present invention it is also to be noted that the piezoresistive effect and the term “piezo MOS effect”, which may occasionally be found in literature, are comparable, since with the piezo MOS effect, essentially just like with the piezoresistive effect, the mobility of the charge carriers in the MOS channel of an MOS field-effect transistor changes under the influence of the mechanical stress present in the semiconductor material of the integrated circuit chip.
It therefore becomes clear that due to mechanical stresses in the semiconductor material of an integrated circuitry, the electrical and/or electronic characteristics of the integrated circuitry could be changed, or negatively affected, in a non-predictable manner, a reduction in the performance, or parameter, of the integrated circuitry being noticeable, e.g., in the form of an impairment of the dynamic range, the resolution, the bandwidth, the power consumption or the accuracy etc.
Specifically, the above-mentioned piezoresistive effect indicates how the specific ohmic resistance ρ of the respective semiconductor material behaves under the influence of a mechanical stress tensor σ and of the piezoresistive coefficients π:ρ=ρ0(1+Σπi,jσi,j)
Here, factor ρ0 is the basic value of the specific resistance which remains unaffected by the mechanical stress.
In integrated circuitries (ICs), the respective current I, e.g. a control current, a reference current etc., is generated by circuit elements of the integrated circuitry on the semiconductor chip. Here, a defined voltage U is produced at an integrated resistor having the resistance R, and current I is decoupled. Current I may generally also be generated at any resistive element, e.g. also at a MOS field-effect transistor located in the linear operating range.
The voltage U may also be created, e.g., by known bandgap principles, in a manner which is relatively constant in relation to mechanical stresses in the semiconductor material (apart from the comparatively small piezojunction effect on the bandgap voltage produced). The resistance R, however, is subject to the piezoresistive effect in accordance with the following relationship:R=R0(1+Σπi,jσi,j)
Here, factor R0 is the basic value of the resistance, which remains unaffected by the mechanical stress, and the value πij is a piezoresistive coefficient. Thus, the current I produced at the resistive element may be expressed as follows:I=U/R=U/(R0(1+Σπijσij))
If the mechanical pressure present on the semiconductor, and thus the mechanical stress present in the semiconductor may be subdivided into an essentially constant basic value σ0ij and a pressure fluctuation δσij which is mostly fairly small and is variable across operating conditions and service life, i.e. may be subdivided into σij=σ0ij±δσij, the current may be expressed as follows, in linear approximation:I=I0(1+Σπijδσij), withI0=U/(R0(1+Σπijσ0ij))
It also becomes clear that the factor taken from the coefficient σij and the pressure fluctuation δσij is problematic and could produce an interference with regard to current I generated, and should come as close to zero as possible.
Since mechanical stresses present in the semiconductor material have an impact on the semiconductor circuit chip, due to the package of the integrated circuitry, in a manner which is difficult to control, the resistance R used for generating current I, and therefore also current I which has been generated, are changed in an undesired and unpredictable manner.
The piezo Hall effect, in contrast, describes the dependence of the Hall constant Rh on the condition of mechanical stress in the semiconductor material, with:Rh=Rh0(1+ΣPi,jσi,j)
σij is the mechanical stress tensor, Pij are the piezo Hall coefficients, the summation extending across i=1 . . . 3 and j=1 . . . 3 with the piezo Hall effect (and the piezoresistive effect).
Both the piezoresistive effect and the piezo Hall effect are highly disruptive in the operation of integrated circuitry, in particular a sensor array, such as an integrated Hall probe, including control electronics and evaluation electronics.
Due to the piezo Hall effect, which occurs in the semiconductor material of the semiconductor chip of the integrated circuitry also as a result of mechanical stresses, the current-related sensitivity Si of the Hall probe changes as follows, e.g. in the case of a Hall probe array:
      S    i    =                    U        h                              I          H                ⁢        B              =                            R          h                t            ⁢      g      Uh is the Hall voltage present at the output side of the Hall probe, IH is the current (control current) flowing through the Hall probe, B is the magnetic flux density to be detected, t is the effective thickness of the active layer of the Hall probe, and g is a geometry factor describing the influence of the contact electrodes on the Hall voltage.
As a result of the piezoresistive effect in the presence of mechanical stresses in the semiconductor material of the Hall-probe array, Hall current IH flowing through the Hall probe will change, since Hall current IH (control current) is defined, in addition, for example, only across a co-integrated resistance R where a voltage U is made to drop, possibly by means of a control loop. A change in the Hall current IH due to the change in the resistance as a result of the piezoresistive effect therefore leads to a change in the sensitivity S of the Hall probe, since the sensitivity S of the Hall probe is identical with the product of the current-related sensitivity Si times the Hall current IH:S=SiIH=Uh/B∞Si/R 
The magnetic sensitivity of the Hall probe S may be defined (as indicated above) as the ratio of the output voltage UH of the Hall probe to the operating magnetic-field component B.
A mechanical stress σij present in the semiconductor material of the Hall-probe array therefore influences the current-related magnetic sensitivity Si of a Hall probe in accordance withSi=Si0(1+ΣPijσij)
Factor Si0 is the basic value of the current-related magnetic sensitivity, which remains unaffected by the mechanical stress, and factor Pij is a piezo Hall coefficient.
Generally, attempts have been made at keeping the magnetic sensitivity S of a Hall probe as constant as possible, with influences due to mechanical stress due to the piezoresistive effects and piezo Hall effects set forth above being disruptive, in particular.
With regard to integrated Hall sensor circuitries generating a switching signal dependent on the operating magnetic-field component B, one should take into account that the magnetic switching threshold Bs may always be returned to the following form:BS∞R/Si 
Thus, it can generally be said that the ratio of the current-related magnetic sensitivity Si to a resistance R is decisive for the magnetic parameters, such as the sensitivity or the switching thresholds of a Hall-probe array.
Eventually, mechanical stresses in the semiconductor material of an integrated circuitry thus have a negative influence on the magnetic sensitivity and/or the switching thresholds of a total system structured by a Hall-probe array.
In practice, magnetic switching sensors show, prior to the packaging process (i.e. on a wafer plane), switching thresholds which differ by about 10% from those switching thresholds after accommodation in a package. The reasons for this are the above-mentioned piezo effects. In particular, after being accommodated in a package, an undesired behavior of the “magnetic switching thresholds versus temperature” in the form of a hysteresis loop may be observed, which opens between 1% and 4%, this being observable, in particular, if the IC package had absorbed a lot of moisture prior to or during the packaging process and if the dwelling time of the semiconductor circuit chip with temperatures above 100° C. is more than 10 minutes (this is typically the diffusion time constant of small packages for integrated circuits). The reasons for this are, again, the above-mentioned piezo effects.
With regard to the piezo effects represented above it should be noted that the coefficients σij, Pij and πij defining the mechanical stresses occurring in the semiconductor material are so-called “tensors”, i.e. that the current-related magnetic sensitivity Si of a Hall element and the resistance R of a resistive element do change not only because of the magnitude of the mechanical stress in the semiconductor material, but also because of the direction of the stress in the semiconductor material. The pronounced directional dependence of the influence of a mechanical stress present in the semiconductor material on electrical and electronic parameters of an integrated circuitry have been known in the art. Thus, the scientific publication [1] “Anisotropy of the Piezojunction Effect in Silicon Transistors” by Creemer, J. F.; French, P. J. in Technical Digest MEMS 2002, the 15. IEEE international conference on Micro Electro Mechanical Systems, Las Vegas, pp. 316 ff, relates to the anisotropy of the piezojunction effect in silicon transistors.
The piezojunction effect indicates how mechanical stresses present in a semiconductor material lead to a shift of the energy level of the band edges of the semiconductor material which result, among other things, in changes in the characteristics of diodes and bipolar transistors.
When mounting an integrated semiconductor circuit chip (IC) in a plastic package, mechanical stresses occur in the semiconductor material of the integrated semiconductor circuit chip, as described above. The mechanical stress present in the semiconductor material influences, by means of the piezojunction effect, the saturation current IS due to changes in the mobility of the minority carriers Δμ and changes in the intrinsic charge-carrier concentration Δni:
            Δ      ⁢                          ⁢              I        S                    I      S        ≅                    Δ        ⁢                                  ⁢        μ            μ        +                  Δ        ⁢                                  ⁢                  n          i          2                            n        i        2            
By means of the known exponential characteristics, the collector current or the base-emitter voltage of a transistor is influenced:
      I    C    =            I      S        ⁢          exp      ⁡              (                              qV            BE                    kT                )            VBE is the base-emitter voltage of a bipolar transistor, q is the elementary charge, and T is the absolute temperature. These connections have been well known in literature. The scientific publication [2]“The piezojunction effect in NPN and PNP vertical transistors and its influence on silicon temperature sensors” by Fabiano Fruet, Guijie Wang, Gerard C. M. Meijer in Sensors and Actuators 85 (2000) 70-74 relates to the piezojunction effect in vertical npn- and pnp-type transistors and its influence on silicon temperature sensors.
If, for example, a bipolar transistor is used for a constant-voltage source, the bandgap voltage VBG of the constant-voltage source is influenced by the piezojunction effect and by the piezoresistive effect because of the mechanical stress in the semiconductor material. The base-emitter voltage VBE of the bipolar transistor contained in the constant-voltage source changes because of the piezojunction effect and also because of the piezoresistive effect, since the resistances of the resistors contained in the constant-voltage source are influenced by the piezoresistive effect.
The bandgap voltage VBG is formed, as is known, by the base-emitter voltage VBE and the temperature voltage VPTAT (PTAT=voltage proportional to the absolute temperature), the negative temperature dependence of the base-emitter voltage VBE being compensated for by a positive temperature dependence of the temperature voltage VPTAT (=ΔVBE). The temperature voltage VPTAT is essentially independent of piezo effects since the temperature voltage VPTAT is formed only by current-density ratios in the bipolar transistors, it being possible to adjust the current-density ratios in a very precise and constant manner by means of layout and design measures. In contrast, the currents in bandgap circuits, however, are in turn defined by resistors, which are subject to piezoresistive effects due to mechanical stresses present in the semiconductor material, e.g. due to being accommodated in a package. Taking into account the piezoresistive effect on the resistance of the integrated resistor (resistive element), the temperature current (IPTAT) may be expressed as follows:
      I    PTAT    =            V      PTAT              R      1      
Accordingly, the following applies to current IVBE, which is formed by means of a base-emitter voltage VBE and a resistance R2 of a further resistor:
      I    VBE    =            V      BE              R      2      
Here, too, mechanical stresses present in the semiconductor material have an effect on the semiconductor circuit chip which is difficult to control, since humidity, material constants and geometries of the packages may vary. Thereby, both the resistance of the reference resistor for generating the operating current flowing through the bandgap circuit, as well as the base-emitter voltage VBE used in the bandgap circuit, and thus the stability of the constant voltage (bandgap voltage), VBG, are changed in an undesired manner.
The bandgap principle is used, for example, with temperature sensors due to its technological robustness. Due to the above-mentioned piezo effects, however, both the reference resistance for generating the operating currents in such a temperature sensor, and the base-emitter voltage VBE used in the temperature sensor, and thus the stability of the temperature measurement, i.e., for example, long-term drift, influence of humidity etc., are changed in an undesired manner by means of scattering due to the fact that the integrated semiconductor circuit chip is accommodated in a plastic package.
Prior to the wafer-level packaging process, i.e. prior to being accommodated in a package, bandgap circuits exhibit voltage values differing by about 0.5 to 2% from the voltage values established once the bandgap circuits are accommodated in a package, the reason for this being the so-called piezo effects. Accordingly, prior to the wafer-level packaging process, temperature sensors exhibit temperature readings (or with temperature switches, temperature threshold values) differing by about 1-5° C. from temperature sensors accommodated in the package due to the above-mentioned piezo effects.
Since the factors σij, Pij and πij represented in the above formulae are so-called tensors, the base-emitter voltages VBE and the resistances R which are used in the bandgap circuit change not only due to the quantities of the respective mechanical stresses, but also due to the direction of the stresses in relation to the semiconductor material. With regard to examinations with regard to the directional dependence, reference shall be made to the scientific publications mentioned below. The directional dependence of the mechanical stress in the semiconductor material applies to the {100} silicon material for p- and n-doped resistors, which is used for the most part. In addition, it is to be noted that {100} wafers and {001} wafers correspond to one another, for reasons of symmetry, in cubic crystals. In the literature mentioned below, both notations are used. For the piezojunction effect of parasitic vertical pnp substrate transistors, which are used, for the most part, in modern CMOS technologies, there are also known figures for stress dependence. Stress dependence is non-directional essentially for in-plane normal, or direct, stress (main-axis stress components on the chip level) in a {100} material for vertical bipolar transistors. Because of the stress dependence of the saturation current of a bipolar transistor, the base-emitter voltage VBE becomes stress-dependent, in dependence on the collector current IC, essentially across the logarithmic characteristic, so that:UBE=ƒ(Ic)
Below, a brief explanation will be given of how attempts have been made, in accordance with the prior art, at reducing the above disruptive piezo influences. It has been known in the art that with {100} silicon material, the mechanical stress dependence of integrated resistors may be reduced by using p-doped resistors instead of n-doped resistors as much as possible, since p-doped integrated resistors generally have smaller piezo coefficients. In addition, n-type resistors are oriented, in general, such that the major part of the current flow flows in a <110> direction, whereas p-type resistors, in contrast, are rotated by an angle of 45° thereto, since p-type resistors generally have smaller piezo coefficients in <100> directions.
In addition, the art has known arrangements, wherein two nominally equal resistors are arranged to be perpendicular to one another and to have a small distance from one another in the layout, and are electrically connected in series or in parallel. Thereby, the total resistance becomes as independent as possible of the direction of the mechanical stress present in the semiconductor material, and therefore becomes reproducible as much as possible. At the same time, the piezo sensitivity of such an arrangement for any direction of the mechanical stress will also become minimal.
In addition, efforts have been made in the art to configure the IC package such that the mechanical stresses acting upon the semiconductor circuit chip may become easier to reproduce. To this effect, the art has either used expensive ceramic packages, or the mechanical parameters of the package components, i.e. semiconductor circuit chip, lead frame, sealing compound, adhesive material or soldering material, are matched such that the influences of the different package components compensate for one another as much as possible or are at least as constant as possible with regard to assembly batch and stress load of the integrated circuitry on the fly. However, it should become clear that matching the mechanical parameters of the package components is extremely expensive, and that, in addition, the slightest changes in the progress of the process again will lead to a change in the influences of the various package components.
Up to now, efforts have been made, in the prior art, to reduce the above-mentioned piezo influences on bandgap circuits by means of suitable devices, e.g. vertical pnp transistors and polysilicon resistors or silicon-chrome resistors, and, additionally, by means of suitable package techniques, e.g. ceramic packages, low-stress plastic materials, grain size of the filler material in plastic, etc., all of which has also been supposed to reduce influences due to humidity and lifetime drift.
The scientific publication [3]“Voltage Shift in Plastic-Packaged Bandgap References” by Buddhika Abesingha, Gabriel A. Rincón-Mora and David Briggs in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 49, No. 10, OCTOBER 2002, pp. 681 relates to voltage shifts of bandgap reference voltage sources accommodated in a plastic package. The scientific publication [4]“Minimization of the Mechanical-Stress-Induced Inaccuracy in Bandgap Voltage References” by Fabiano Fruett, Gerard C. M. Meijer, and Anton Bakker in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 38, No. 7, JULY 2003, pp. 1288-1291, relates to minimizing the inaccuracies caused by mechanical stress in bandgap reference voltage sources by using vertical pnp transistors and chopper techniques.
The scientific publication [5] “Compensation for piezoresistivity effect in p-type implanted resistors” by F. Fruett, G. C. M. Meijer in Electronic letters 2 September 1999, Vol. 35, No. 18, pp. 1587, relates to the compensation for the piezoresistive effect in implanted p-type resistors.
The above illustrations and the above-mentioned scientific publications clearly show that an influence, which is undesired and difficult to control, on the physical functional parameters of semiconductor devices of integrated circuitries on a semiconductor circuit chip may be caused by mechanical stresses in the semiconductor material by means of various piezo effects. A compensation for the influence of the piezo effects on the physical and electronic functional parameters of the semiconductor devices is problematic in that the stress components occurring in the semiconductor material are generally neither known in advance, nor do they remain constant during the life period, so that when the integrated circuitry is accommodated in a package, the mechanical parameters, i.e., for example, the material of the semiconductor chip, the lead frame, the sealing compound, the adhesive or the solder material, are difficult or impossible to match with one another so as to check the above-mentioned piezo influences on the semiconductor material, and, thus, on the electronic and physical functional parameters of the semiconductor devices in a suitable manner.